1. Field of the Invention
The present invention relates to a semiconductor device having a multilayer printed wiring board where a semiconductor chip is provided and a manufacturing method of the same.
2. Description of the Related Art
Recently and continuing, as performance and function of large scale integrated circuits (LSI) are becoming high, it is desired that mounting substrates have small size, high density and a large number of pins. A built-up multilayer substrate wherein wiring layers and dielectric layers are reciprocally stacked is being utilized as a high density mounting substrate.
The built-up multilayer substrate is formed by repeating processes for making multilayers, that is, repeating a process for forming a dielectric layer made of epoxy group resin on a glass epoxy substrate which is a core substrate and then a process for forming a via forming part piercing the dielectric layer and a wiring layer made of an internal layer conductive pattern.
As the speed implemented by the LSI is becoming high, it is required that a transfer speed between the LSIs be high and therefore a high frequency transfer property in the built-up multilayer substrate is required. In the built-up multi layer substrate, decoupling capacitors are provided around the LSI. The decoupling capacitor has a function to transiently flow an overcurrent generated at the time when a digital circuit of the LSI is being switched. By flowing the overcurrent, a state transition of a signal from “low” to “high” is implemented, and vice versa, so that a signal delay is suppressed. The decoupling capacitor also has a function to prevent energy of the over-current from being diffused into the whole of the substrate so as to prevent generation of noise due to the diffusion of the energy.
For example, in a semiconductor package of the related art, an opening part is provided at a metal core and an LSI chip is fixed to the opening part. In addition, a built-up multilayer substrate is provided on the surface of the metal core around the opening part. Under this structure, the chip and the built-up multilayer substrate are connected by a wire. See Japan Laid-Open Patent Publication No. 5-226513 and Japan Laid-Open Patent Publication No. 2000-133745.
In the case of the above-mentioned semiconductor package, the wiring length between the chip and the decoupling capacitor mounted on the built-up multilayer substrate is long and signal noise is generated. Furthermore, an inductance component generated at the wiring increases. A resonance circuit is formed by a capacity value of the decoupling capacitor and the inductance component and a resonant frequency is reduced. As a result of this, a high frequency transmission property is degraded.
To solve the above-mentioned problem, a semiconductor package 100 is suggested, as shown in FIG. 1, in the publication, “Bumpless Built-Up Layer Packaging”, Gilroy J. Vandentop et. al., ASME International Mechanical Engineering Congress and Exposition (IMECE), Nov. 11, 2001. As shown in FIG. 1-(A), an LSI chip 101 is provisionally fixed to a film support body 107 by using an opening part 102a of a support substrate 102 and then fixed to the film support body 107 by resin 109. As shown in FIG. 1-(B), a built-up multilayer substrate 103 is formed on a surface at a side of electrodes 108 of the LSI chip 101 so that a decoupling capacitor 104 is mounted.
Furthermore, a semiconductor package 110 is suggested, as shown in FIG. 2, in the publication “High-Performance Flip-Chip BGA based on Multi-Layer Thin-Film Packaging Technology”, T. Shimoto et. al., Proceedings of the 2002 IMAPS, p. 10-15. In the semiconductor package 110, a built-up multilayer substrate 112 is formed on a metal plate 111. After an LSI chip 101 is connected to the built-up multilayer substrate 112, the whole surface of the metal board 111 is removed.
However, in the semiconductor package 100 shown in FIG. 1-(B), the built-up multi layer substrate 103 is formed on the LSI chip 101 fixed to the opening part 102a of the support substrate 102. Therefore, disconnection between the electrodes 108 of the LSI chip 101 and the wiring layer 103b may be generated, due to a difference of the coefficient of thermal expansion between the LSI chip 101 and the dielectric layer 103a, by a heating process at the time when the dielectric layer 103a and the wiring layer 103b are stacked or solder bumps 105 or pins 106 are connected.
Furthermore, when the LSI chip 101 is fixed in the opening part 102a, the position of the LSI chip 101 varies widely against the opening part 102a. Therefore, it is difficult to position the wiring layer 103b to connect the electrodes 108 of the LSI chip 101. Furthermore, if the yield rate of the built-up multilayer substrate 103 itself is reduced, since it is difficult to reuse the LSI chip 101, the semiconductor chip may be useless and therefore manufacturing cost may be increased.
In addition, to make the semiconductor package 110 shown in FIG. 2, it is necessary to perform a process for removing the metal plate 111 after the LSI chip 1-1 is solder-connected to the built-up multilayer substrate 112. Therefore, the process may be complicated from the perspective of a control of a temperature condition or protection of the LSI chip 101. Furthermore, although a stiffener 114 is provided in the semiconductor package 110, a curve or winding, different from one at the time of fabrication of the built-up multilayer substrate 112, may be generated after the metal plate 111 is removed. Hence, it may be difficult to handle this at the time when the semiconductor package 110 is mounted.